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78M6610+PSU Data Sheet
The second type of transaction is dedicated to transporting data between the host and the device and is
structured as follows:
Byte
Number
1
2
3
4
5
6
7
…
(NbrAcc *3)
(NbrAcc*3)+1
(NbrAcc*3)+2
(NbrAcc*3)+3
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
ADDR[5:0] R/W
DATA[23:16] @ Addr
DATA[15:8] @ Addr
DATA[7:0] @ Addr
DATA[23:16] @ Addr + 1
DATA[15:8] @ Addr +1
DATA[7:0] @ Addr +1
…
DATA[7:0] @ Addr + NbrAcc
DATA[23:16] @ Addr + NbrAcc
DATA[15:8] + NbrAcc
DATA[7:0] + NbrAcc
Bit 0
0
R/W: Defines the directionality of the transaction (Read = 0; Write = 1);
ADDR[5:0]: Indicates the remainder of the address to access.
The following are some transaction examples.
Example 1: Write access of address 0x14.
Byte
Number
1
Bit 7
Bit 6 Bit 5
NbrAcc[3:0] = 0x00
Bit 4
Bit 3
Addr7=0
Bit 2
Addr6=0
Bit 1
0
Bit 0
1
2
3
4
5
Addr[5:0] = 0x14
Data[23:16] @ 0x14
Data[15:8] @ 0x14
Data[7:0] @ 0x14
WR=1
0
Example 2: Read access of address 0x17 and 0x18.
Byte
Number
1
2
3
4
5
6
7
8
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3
NbrAcc[3:0] = 0x01 Addr7=0
Addr[5:0] = 0x17
Data[23:16] @ 0x17
Data[15:8] @ 0x17
Data[7:0] @ 0x17
Data[23:16] @ 0x18
Data[15:8] @ 0x18
Data[7:0] @ 0x18
Bit 2
Addr6=0
Bit 1
0
RD=0
Bit 0
1
0
Rev 1
47
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